The manufacture of integrated circuits in a semiconductor device involves the formation of a sequence of layers that contain metal wiring. Metal interconnects and vias which form horizontal and vertical connections in the device are separated by insulating layers or inter-level dielectric layers (ILDs) to prevent crosstalk between the metal wiring that can degrade device performance. A popular method of forming an interconnect structure is a dual damascene process in which vias and trenches are filled with metal in the same step to create multi-level, high density metal interconnections needed for advanced high performance integrated circuits. The most frequently used approach is a via first process in which a via is formed in a dielectric layer and then a trench is formed above the via. Recent achievements in dual damascene processing include lowering the resistivity of the metal interconnect by switching from aluminum to copper, decreasing the size of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of insulators or ILDs by using so-called low k materials to avoid capacitance coupling between the metal interconnects. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9. One class of low-k material that have been explored are organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD.
One important step in the dual damascene fabrication process is the application of organic photoresist material as a precursor to formation of features such as vias and trenches on a substrate using photolithographic techniques. Often additional coatings, for example an anti-reflective coating known in the industry as BARC (Bottom Antireflective Coating), are applied to the substrate to enhance the lithography process.
Once lithography is completed, the resist, BARC and other coatings used for the lithography steps must be removed from the substrate. Undesired resist and/or resist residue can have deleterious effects on subsequent processes such as metallization, or cause undesirable surface states and charges. A common technique for photoresist removal involves placing the substrate in an asher and burning the resist and associated coatings using a gaseous plasma. While the high temperature in the plasma process chamber oxidizes the photoresist and removes it, the plasma etch process leaves post-ash residues—undesirable byproducts from the reaction of the plasma gases, reactant species and the photoresist. The plasma gases that may be used include N2/H2, N2/O2, O2/CO, and O2/Ar, for example.
The plasma etch procedure for resist removal is less desirable for substrates having organic low k films as insulating layers. In particular, these insulating layers are porous and are thus more likely to absorb etch gases which can later out-gas and attack metal contacts formed into the substrate (e.g., dual damascene copper). In addition, etchants can damage the organic low k films by the removal of carbon.
Accordingly, it would be desirable to provide a dual damascene interconnect in which photoresist can be removed without a deleterious affect on the underlying low k layer.